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PH955L
N-channel TrenchMOS logic level FET
Rev. 02 -- 19 February 2009 Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only.
1.2 Features and benefits
Low conduction losses due to low on-state resistance Suitable for logic level gate drive sources
1.3 Applications
DC-to-DC convertors General purpose power switching Motors, lamps and solenoids Portable equipment
1.4 Quick reference data
Table 1. VDS ID Ptot Quick reference Conditions Tmb = 25 C; VGS = 5 V; see Figure 1; see Figure 3 Tmb = 25 C; see Figure 2 Min Typ Max 55 62.5 62.5 Unit V A W drain-source voltage Tj 25 C; Tj 150 C drain current total power dissipation gate-drain charge Symbol Parameter
Dynamic characteristics QGD VGS = 5 V; ID = 25 A; VDS = 44 V; Tj = 25 C; see Figure 11; see Figure 12 VGS = 10 V; ID = 25 A; Tj = 25 C; see Figure 10 16.4 nC
Static characteristics RDSon drain-source on-state resistance 6.2 8.3 m
NXP Semiconductors
PH955L
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2. Pin 1 2 3 4 mb S S S G D Pinning information Symbol Description source source source gate mounting base; connected to drain
mbb076
Simplified outline
mb
Graphic symbol
D
G S
1234
SOT669 (LFPAK)
3. Ordering information
Table 3. Ordering information Type number Package Name Description PH955L LFPAK plastic single-ended surface-mounted package (LFPAK); 4 leads
Version SOT669
PH955L_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 19 February 2009
2 of 13
NXP Semiconductors
PH955L
N-channel TrenchMOS logic level FET
4. Limiting values
Table 4. Symbol VDS VDGR VGS ID IDM Ptot Tstg Tj IS ISM EDS(AL)R EDS(AL)S Limiting values Parameter drain-source voltage drain-gate voltage gate-source voltage drain current peak drain current total power dissipation storage temperature junction temperature source current peak source current repetitive drain-source avalanche energy Tmb = 25 C tp 10 s; pulsed; Tmb = 25 C VGS = 5 V; ID = 4.4 A; Vsup 55 V; unclamped; tp = 0.1 ms; RGS = 50 [1][2] VGS = 5 V; Tmb = 100 C; see Figure 1 VGS = 5 V; Tmb = 25 C; see Figure 1; see Figure 3 tp 10 s; pulsed; Tmb = 25 C; see Figure 3 Tmb = 25 C; see Figure 2 Conditions Tj 25 C; Tj 150 C Tj 25 C; Tj 150 C; RGS = 20 k Min -20 -55 -55 Max 55 55 20 43.7 62.5 187 62.5 150 150 52 156 2 195 Unit V V V A A A W C C A A mJ mJ
In accordance with the Absolute Maximum Rating System (IEC 60134).
Source-drain diode
Avalanche ruggedness
non-repetitive VGS = 5 V; Tj(init) = 25 C; ID = 44 A; Vsup 55 V; drain-source avalanche unclamped; tp = 0.1 ms; RGS = 50 energy
[1] [2] Duty cycle is limited by the maximum junction temperature.
Repetitive avalanche failure is not determined simply by thermal effects. Repetitive avalanche transients should only be applied for short bursts, not every switching cycle.
PH955L_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 19 February 2009
3 of 13
NXP Semiconductors
PH955L
N-channel TrenchMOS logic level FET
120 Ider (%) 80
03aa24
120 Pder (%) 80
03aa16
40
40
0 0 50 100 150 Tmb (C) 200
0 0 50 100 150 Tmb (C) 200
Fig 1.
Normalized continuous drain current as a function of mounting base temperature
Fig 2.
Normalized total power dissipation as a function of mounting base temperature
003aaa777
103 ID (A) 10
2
Limit RDSon = VDS / ID
tp = 10 s
100 s 10 DC 1 1 ms 10 ms 100 ms
10-1 10-1
1
10
VDS (V)
102
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PH955L_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 19 February 2009
4 of 13
NXP Semiconductors
PH955L
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5. Symbol Rth(j-mb) Thermal characteristics Parameter Conditions Min Typ Max 2 Unit K/W thermal resistance from see Figure 4 junction to mounting base
10 Zth(j-mb) (K/W) 1 = 0.5 0.2 0.1 10-1 0.05 0.02 single pulse 10-2
tp T P
003aaa778
=
tp T
t
10-3 10-5
10-4
10-3
10-2
10-1
tp (s)
1
Fig 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration
PH955L_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 19 February 2009
5 of 13
NXP Semiconductors
PH955L
N-channel TrenchMOS logic level FET
6. Characteristics
Table 6. Symbol V(BR)DSS VGS(th) Characteristics Parameter drain-source breakdown voltage gate-source threshold voltage Conditions ID = 250 A; VGS = 0 V; Tj = -55 C ID = 250 A; VGS = 0 V; Tj = 25 C ID = 1 mA; VDS = VGS; Tj = -55 C; see Figure 7; see Figure 8 ID = 1 mA; VDS = VGS; Tj = 150 C; see Figure 7; see Figure 8 ID = 1 mA; VDS = VGS; Tj = 25 C; see Figure 7; see Figure 8 IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance VDS = 55 V; VGS = 0 V; Tj = 25 C VDS = 55 V; VGS = 0 V; Tj = 150 C VGS = 15 V; VDS = 0 V; Tj = 25 C VGS = -15 V; VDS = 0 V; Tj = 25 C VGS = 4.5 V; ID = 25 A; Tj = 25 C VGS = 10 V; ID = 25 A; Tj = 150 C; see Figure 9 VGS = 10 V; ID = 25 A; Tj = 25 C; see Figure 10 Dynamic characteristics QG(tot) QGS QGS1 QGS2 QGD VGS(pl) Ciss Coss Crss td(on) tr td(off) tf VSD trr Qr
PH955L_2
Min 50 55 0.5 1 -
Typ 1.5 0.02 2 2 7.1 6.2
Max 2.3 2 1 500 100 100 9.9 16 8.3
Unit V V V V V A A nA nA m m m
Static characteristics
total gate charge gate-source charge pre-threshold gate-source charge post-threshold gate-source charge gate-drain charge gate-source plateau voltage input capacitance output capacitance reverse transfer capacitance turn-on delay time rise time turn-off delay time fall time source-drain voltage reverse recovery time recovered charge
ID = 25 A; VDS = 44 V; VGS = 5 V; Tj = 25 C; see Figure 11; see Figure 12
-
42 5.7 4.3 1.4 16.4 2 2836 441 210 18 71 105 25 0.85 62 48
1.2 -
nC nC nC nC nC V pF pF pF ns ns ns ns V ns nC
ID = 25 A; VDS = 44 V; Tj = 25 C; see Figure 11; see Figure 12 VDS = 25 V; VGS = 0 V; f = 1 MHz; Tj = 25 C; see Figure 13
-
VDS = 25 V; RL = 1 ; VGS = 5 V; RG(ext) = 4.7 ; Tj = 25 C
-
Source-drain diode IS = 25 A; VGS = 0 V; Tj = 25 C; see Figure 14 IS = 20 A; dIS/dt = -100 A/s; VGS = 0 V; VDS = 30 V; Tj = 25 C -
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 19 February 2009
6 of 13
NXP Semiconductors
PH955L
N-channel TrenchMOS logic level FET
40 ID (A) 30
003aaa779
10 5 3
2.5
2.3 VGS (V) = 2.2
40 ID (A) 30
003aaa780
2.1 20 2 10 10 20
Tj = 150 C
25 C
0 0 0.5 1 1.5 VDS (V) 2
0 0 1 2 VGS (V) 3
Fig 5.
Output characteristics: drain current as a function of drain-source voltage; typical values
2.5
03aa33
Fig 6.
Transfer characteristics: drain current as a function of gate-source voltage; typical values
03aa36
VGS(th) (V) 2 max
10-1 ID (A) 10-2
1.5
typ
10-3 min typ max
1
min
10-4
0.5
10-5
0 -60
10-6 0 60 120 Tj (C) 180 0 1 2 VGS (V) 3
Fig 7.
Gate-source threshold voltage as a function of junction temperature
Fig 8.
Sub-threshold drain current as a function of gate-source voltage
PH955L_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 19 February 2009
7 of 13
NXP Semiconductors
PH955L
N-channel TrenchMOS logic level FET
2.4 a
03aa28
20 RDSon (m) 16 2 2.1 2.2
003aaa782
2.3
1.8
12
1.2
VGS (V) = 2.5 3
8
0.6
4.5 10
4
0 -60
0
0 60 120 Tj (C) 180
0
10
20
30
ID (A)
40
Fig 9.
Normalized drain-source on-state resistance factor as a function of junction temperature
10
003aaa784
Fig 10. Drain-source on-state resistance as a function of drain current; typical values
VGS (V) 8 VDD = 12 V 6
VDS ID VGS(pl) VGS(th)
44 V
4
VGS QGS1 QGS2 QGD QG(tot)
003aaa508
2
QGS
0 0 20 40 60 QG (nC) 80
Fig 12. Gate charge waveform definitions
Fig 11. Gate-source voltage as a function of gate charge; typical values
PH955L_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 19 February 2009
8 of 13
NXP Semiconductors
PH955L
N-channel TrenchMOS logic level FET
104 C (pF)
003aaa783
40 IS (A)
003aaa781
Ciss
30
150 C 103 20
Tj = 25 C
Coss 10 Crss 102 10-1 0 0.2
1
10
VDS (V)
102
0.4
0.6
0.8
VSD (V)
1
Fig 13. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values
Fig 14. Source current as a function of source-drain voltage; typical values
PH955L_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 19 February 2009
9 of 13
NXP Semiconductors
PH955L
N-channel TrenchMOS logic level FET
7. Package outline
Plastic single-ended surface-mounted package (LFPAK); 4 leads SOT669
E b2 L1
A c2
A2
C E1 b3
mounting base D1 H D
b4
L2
1
e
2
3
b
1/2
4
wM A c X
e
A A1 C
(A 3)
detail X L yC 0 2.5 scale 5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A A1 A2 A3 b b2 b3 2.2 2.0 b4 0.9 0.7 c c2 D (1) D1(1) E(1) E1(1) max 5.0 4.8 3.3 3.1 e 1.27 H 6.2 5.8 L 0.85 0.40 L1 1.3 0.8 L2 1.3 0.8 w 0.25 y 0.1 8 0
1.20 0.15 1.10 0.50 4.41 0.25 1.01 0.00 0.95 0.35 3.62
0.25 0.30 4.10 4.20 0.19 0.24 3.80
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT669 REFERENCES IEC JEDEC MO-235 JEITA EUROPEAN PROJECTION ISSUE DATE 04-10-13 06-03-16
Fig 15. Package outline SOT669 (LFPAK)
PH955L_2 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 19 February 2009
10 of 13
NXP Semiconductors
PH955L
N-channel TrenchMOS logic level FET
8. Revision history
Table 7. PH955L_2 Modifications: Revision history Release date 20090219 Data sheet status Product data sheet Change notice Supersedes PH955L_1 Document ID
* *
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Product data sheet -
PH955L_1 (9397 750 14557)
20050301
PH955L_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 19 February 2009
11 of 13
NXP Semiconductors
PH955L
N-channel TrenchMOS logic level FET
9. Legal information
9.1 Data sheet status
Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Document status [1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
9.2
Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
9.3
Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk.
9.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS -- is a trademark of NXP B.V.
10. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
PH955L_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 19 February 2009
12 of 13
NXP Semiconductors
PH955L
N-channel TrenchMOS logic level FET
11. Contents
1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3 Thermal characteristics . . . . . . . . . . . . . . . . . . .5 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Package outline . . . . . . . . . . . . . . . . . . . . . . . . .10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . .12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Contact information. . . . . . . . . . . . . . . . . . . . . .12
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 19 February 2009 Document identifier: PH955L_2

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